Efficient Architectures for Polar Codes

Institution: University of California, San Diego

Summary
Researchers from UC San Diego, in collaboration with their colleagues at McGill University, have created novel approaches for hardware implementation for the recently developed Polar Codes. These error correction codes are widely considered as a major breakthrough in coding theory. Polar Codes have been theoretically shown to achieve Shannon capacity limits for channels that are symmetric, memory-less, and have binary inputs through successive cancellation decoding. In addition, Polar Codes can be efficiently constructed and efforts are underway to address the issue of their large code lengths. In order to practically implement Polar Codes, hardware architectures must support high throughput in a low complexity, small area implementation.

Description
Three distinct architectures have been developed.

  • Pipelined tree architecture that exploits the scheduling of updates in order to group multiple operations in a single processing element.
  • Line architecture that further reduces the number of processing elements by multiplexing processing elements with registers.
  • Vector overlapping architecture that leverages the processing elements during idle cycles.

Advantage
The current state-of-the-art, successive cancellation decoder is implemented by the factor graph of the code. This structure resembles a Fast Fourier Transform. However, this leads to updating rules that require complex hardware operations, such as mu

Category
Communication;Engineering

Contact Information
University of California, San Diego Technology Transfer Office
invent@ucsd.edu
http://techtransfer.universityofcalifornia.edu/NCD/22034.html

Keywords
compression, error correction, VLSI, signal processing